The present invention relates generally to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device and a manufacturing method thereof, which have characteristics in terms of a structure of a capacitor and in terms of a method of manufacturing this capacitor.
A dynamic DRAM contains capacitors for storing information. These capacitors are arranged in a matrix in a memory device. Among these capacitors, a capacitor in a predetermined position is selected based on address information supplied from outside. The selected capacitor is supplied with information converted into an electric charge by a write control system.
When in a reading process, the capacitor in the predetermined position is selected based on the address information, and the electric charge of the selected capacitor is read to a bit line previously charged by a read control system. This electric charge is amplified by a sense amplifier and then outputted to outside.
FIG. 2 is a diagram of one example of a DRAM memory cell mask pattern, showing a structure of the capacitors in the DRAM having a conventional COB structure. AC areas y1 are formed obliquely in FIG. 2, and bit lines y2 extend in an X-direction while word lines y3 extend in a Y-direction. Hereinafter, mainly an X-directional structure and a manufacturing method thereof will be explained with reference to FIGS. 3, 5 and 7, while a Y-directional structure is shown in FIGS. 4, 6 and 8.
FIG. 3 shows an X-directional section in the middle of a process of manufacturing the capacitor illustrated in FIG. 2. FIG. 4 shows a Y-directional section from FIG. 2. Provided on a substrate 51, composed of a semiconductor such as Si monocrystal or the like, are a field oxide film 52 having a thickness on the order of 2000-4000 A and a MOS transistor (Tr) gate oxide film 53 having a thickness of approximately 50-150 A, which are formed normally by a LOCOS (Local Oxidation of Silicon: Selective Oxidation) method.
After the gate oxide film 53 and the field oxide film 52 have been formed, a plurality of electrodes 54 supplied with signals for capacitors are provided on these films. Then, insulating oxide films 55 are provided on both sides of these electrodes 54. The electrode 54 composed of polysilicon or polycide is formed to a thickness of approximately 1000-2000 A and subjected to patterning in the Y-direction by ordinary photolithography and etching.
After the electrodes 54 and the oxide films 55 have been formed, BPSG (borophosphosilicate glass) films 56 are formed thereon by a CVD (Chemical Vapor Deposition) method. This BPSG film 56 is formed with a hole 57 penetrating the BPSG film 56 and the gate oxide film 53, through which the substrate 51 is exposed. Provided also is an electrode 58 connected to the substrate 51 exposed through the hole 57. The electrode 58, composed of polysilicon and polycide, is subjected to X-directional patterning by ordinary photolithography as well as by etching, and is thus formed.
Thereafter, as illustrated in FIG. 5, a resist pattern 60 is formed by ordinary photolithography, and a hole 61 is obtained (a Y-directional section is shown in FIG. 6) by etching. Next, as shown in FIG. 7, a polysilicon layer 62 that is approximately 5000-10000 A in thickness is provided as an electrode layer serving as one plate of the capacitor. Thereafter, a Si3N film 63, serving as a dielectric layer of the capacitor, is formed to a thickness on the order of 30-100 A on the surface of the electrode layer 62, and a polysilicon layer 64, serving as the other plate of the capacitor, is formed to a thickness of approximately 1000-2000 A on the Si3N film 63. The capacitor is thus completed. FIG. 8 illustrates a Y-directional section of this capacitor.
In the construction described above, however, an area of the memory cell contact 61 of the DRAM can not be enlarged when reducing the device, and hence there arises a problem of causing an increase in the number of steps for enlarging the capacitor area. Another problem is that a hole margin of the photolithography process of the memory cell contact is small.
It is a primary object of the present invention, which was contrived to obviate the problems given above, to provide a semiconductor device and a manufacturing method thereof, which are capable of enlarging an area of a DRAM memory cell contact.
It is another object of the present invention to provide a semiconductor device and a manufacturing method thereof, which are capable of increasing a hole margin of a photolithography process of a memory cell contact.
A semiconductor device according to the present invention comprises a semiconductor substrate, a gate electrode formed on the semiconductor substrate and extending in a first direction, a first protection layer formed along a side wall of the gate electrode as well as on the gate electrode and exhibiting an insulating property, an inter-layer insulating layer formed on the semiconductor substrate including the first protection layer, having an opening portion extending to the first protection layer and to the semiconductor substrate as well and exhibiting a selectivity for the first protection layer when in an etching process, and a capacitor formed inwardly of the opening portion.
The first protection layer may be, e.g., a nitride layer, and the inter-layer insulating layer may be, e.g., an oxide layer.
Further, the capacitor may be constructed of a first conductive layer connected to the semiconductor substrate and having a rugged surface, a capacitor insulating film formed on the first conductive layer, and a second conductive layer formed on the capacitor insulating film.
Alternatively, the inter-layer insulating layer may be constructed of a first insulating layer and a second insulating layer formed on the first insulating layer. The inter-layer insulating layer may contain a bit line provided between the first insulating layer and the second insulating layer and extending in a direction substantially orthogonal to the first direction, and a second protection layer provided on the bit line and along a side wall of the bit line and exhibiting a selectivity with respect to the inter-layer insulating layer when in an etching process and also an insulating property. The opening portion may extend to the second protection layer.
A semiconductor device manufacturing method according to the present invention is used for manufacturing the semiconductor device according to the present invention.
This manufacturing method comprises a step of forming a gate insulating film and a gate electrode extending in a first direction on a semiconductor substrate, a step of forming a protection layer exhibiting an insulating property on an upper portion of the gate electrode and along a side wall thereof, a step of forming a inter-layer insulating layer on the semiconductor substrate including the protection layer, a step of forming an opening portion extending to the protection layer and to the semiconductor substrate by selectively etching the inter-layer insulting layer, and a step of forming a capacitor inwardly of the opening portion.